/*
 * Copyright (C) 2018 Unigroup Spreadtrum & RDA Technologies Co., Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2018-12-18 10:53:49
 *
 */


#ifndef ANLG_PHY_G3_H
#define ANLG_PHY_G3_H

#define CTL_BASE_ANLG_PHY_G3 0x323B0000


#define REG_ANLG_PHY_G3_ANALOG_26MBUF_26MBUF_CTRL0             ( CTL_BASE_ANLG_PHY_G3 + 0x0000 )
#define REG_ANLG_PHY_G3_ANALOG_USB20_USB20_TEST_PIN            ( CTL_BASE_ANLG_PHY_G3 + 0x0004 )
#define REG_ANLG_PHY_G3_ANALOG_USB20_USB20_UTMI_CTL1           ( CTL_BASE_ANLG_PHY_G3 + 0x0008 )
#define REG_ANLG_PHY_G3_ANALOG_USB20_USB20_BATTER_PLL          ( CTL_BASE_ANLG_PHY_G3 + 0x000C )
#define REG_ANLG_PHY_G3_ANALOG_USB20_USB20_UTMI_CTL2           ( CTL_BASE_ANLG_PHY_G3 + 0x0010 )
#define REG_ANLG_PHY_G3_ANALOG_USB20_USB20_TRIMMING            ( CTL_BASE_ANLG_PHY_G3 + 0x0014 )
#define REG_ANLG_PHY_G3_ANALOG_USB20_USB20_PLL_CTRL            ( CTL_BASE_ANLG_PHY_G3 + 0x0018 )
#define REG_ANLG_PHY_G3_ANALOG_USB20_USB20_PHY_BIST_TEST       ( CTL_BASE_ANLG_PHY_G3 + 0x001C )
#define REG_ANLG_PHY_G3_ANALOG_USB3_TYPEC_ANA_USB30_CTRL2      ( CTL_BASE_ANLG_PHY_G3 + 0x0028 )
#define REG_ANLG_PHY_G3_ANALOG_USB3_TYPEC_ANA_USB30_CTRL3      ( CTL_BASE_ANLG_PHY_G3 + 0x002C )
#define REG_ANLG_PHY_G3_ANALOG_USB3_TYPEC_ANA_USB31_CTRL4      ( CTL_BASE_ANLG_PHY_G3 + 0x0030 )

/* REG_ANLG_PHY_G3_ANALOG_26MBUF_26MBUF_CTRL0 */

#define BIT_ANLG_PHY_G3_ANALOG_26MBUF_REC_26MHZ_CUR_SEL(x)      (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G3_ANALOG_26MBUF_REC_26MHZ_RESERVED(x)     (((x) & 0x3FF) << 2)
#define BIT_ANLG_PHY_G3_ANALOG_26MBUF_REC_26MHZ_BG_RBIAS_MODE   BIT(1)
#define BIT_ANLG_PHY_G3_ANALOG_26MBUF_REC_26MHZ_TEST_EN         BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_USB20_USB20_TEST_PIN */

#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_TESTCLK              BIT(18)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_TESTDATAIN(x)        (((x) & 0xFF) << 10)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_TESTADDR(x)          (((x) & 0xF) << 6)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_TESTDATAOUTSEL       BIT(5)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_BIST_MODE(x)         (((x) & 0x1F))

/* REG_ANLG_PHY_G3_ANALOG_USB20_USB20_UTMI_CTL1 */

#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_DATABUS16_8          BIT(22)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_RXERROR              BIT(21)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_BYPASS_DRV_DP        BIT(20)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_BYPASS_DRV_DM        BIT(19)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_BYPASS_IN_DP         BIT(18)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_BYPASS_OUT_DM        BIT(17)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_VBUSVLDEXT           BIT(16)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_RESERVED(x)          (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_USB20_USB20_BATTER_PLL */

#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_REXTENABLE           BIT(2)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_DMPULLUP             BIT(1)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_SAMPLER_SEL          BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_USB20_USB20_UTMI_CTL2 */

#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_TXBITSTUFFENABLE     BIT(1)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_TXBITSTUFFENABLEH    BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_USB20_USB20_TRIMMING */

#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_TUNEHSAMP(x)         (((x) & 0x3) << 25)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_TFREGRES(x)          (((x) & 0x3F) << 19)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_TFHSRES(x)           (((x) & 0x1F) << 14)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_TUNERISE(x)          (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_TUNEOTG(x)           (((x) & 0x7) << 9)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_TUNEDSC(x)           (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_TUNESQ(x)            (((x) & 0xF) << 3)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_TUNEEQ(x)            (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_USB20_USB20_PLL_CTRL */

#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_TUNEPLLS(x)          (((x) & 0xF) << 10)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_PLL_PFD_DEADZONE(x)  (((x) & 0x3) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_PLL_PFD_DELAY(x)     (((x) & 0x3) << 6)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_PLL_CP_IOFFSET_EN    BIT(5)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_PLL_CP_IOFFSET(x)    (((x) & 0xF) << 1)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_PLL_REF_DOUBLER_EN   BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_USB20_USB20_PHY_BIST_TEST */

#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_BISTRAM_EN           BIT(1)
#define BIT_ANLG_PHY_G3_ANALOG_USB20_USB20_BIST_MODE_EN         BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_USB3_TYPEC_ANA_USB30_CTRL2 */

#define BIT_ANLG_PHY_G3_ANALOG_USB3_TYPEC_USB30_RESERVEDIN(x)   (((x) & 0xFFFF) << 16)
#define BIT_ANLG_PHY_G3_ANALOG_USB3_TYPEC_USB30_RESERVEDOUT(x)  (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_USB3_TYPEC_ANA_USB30_CTRL3 */

#define BIT_ANLG_PHY_G3_ANALOG_USB3_TYPEC_USB30_TRIM_RXRCTL(x)  (((x) & 0xF) << 9)
#define BIT_ANLG_PHY_G3_ANALOG_USB3_TYPEC_USB30_TRIM_BG(x)      (((x) & 0xF) << 5)
#define BIT_ANLG_PHY_G3_ANALOG_USB3_TYPEC_USB30_TRIM_TXRCTL(x)  (((x) & 0x1F))

/* REG_ANLG_PHY_G3_ANALOG_USB3_TYPEC_ANA_USB31_CTRL4 */

#define BIT_ANLG_PHY_G3_ANALOG_USB3_TYPEC_UTMISRP_BVALID        BIT(0)


#endif /* ANLG_PHY_G3_H */


